1. Field of the Invention
This invention relates to magnetic memory arrays and, more particularly, to data line configurations within magnetic memory cells.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Recently, advancements in the use of magnetoresistive materials have progressed the development of magnetic random access memory (MRAM) devices to function as viable non-volatile memory circuits. In general, MRAM circuits exploit the electromagnetic properties of magnetoresistive materials to set and maintain information stored within individual magnetic memory cell junctions of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a magnetic junction, and differential resistance measurements to read information from the magnetic junction. In general, an MRAM circuit includes one or more conductive lines with which to generate magnetic fields such that the magnetization directions of one or more magnetic junctions of the MRAM circuit may be set. Consequently, in some embodiments, the conductive lines may be referred to as xe2x80x9cfield-inducing lines.xe2x80x9d
Typically, the conductive lines are formed as substantially straight and uniform structures of metal spaced parallel and perpendicular to each other within a plane comprising the magnetic cell junctions. In other words, the conductive lines are generally arranged in series of columns and rows having magnetic junctions interposed at the overlap points of the conductive lines. In this manner, the circuit may include a plurality of memory cells arranged within an array. In some cases, the conductive lines may be referred to as xe2x80x9cbitxe2x80x9d and xe2x80x9cdigitxe2x80x9d lines. In general, xe2x80x9cbitxe2x80x9d lines may refer to the conductive lines that are arranged in electrical contact with magnetic junctions. xe2x80x9cDigitxe2x80x9d lines, on the other hand, may refer to the conductive lines spaced vertically adjacent to the magnetic junctions and, therefore, are not arranged in electrical contact with the magnetic junctions. In general, bit lines are used for both the write and read operations of the array, while the digit lines are used primarily during write operations of the array.
In general, an individual magnetic junction can be written to by applying current simultaneously along a bit line and a digit line corresponding to the particular magnetic junction. Such an individual magnetic junction may herein be referred to as a selected magnetic junction, or the magnetic junction intentionally targeted for a writing procedure. During the writing procedure, however, the multitude of other magnetic junctions arranged vertically adjacent to the bit line and the digit line corresponding to the selected junction will also sense current. Such magnetic junctions are herein referred to as half-selected junctions, or disturbed junctions since the magnetic field induced about them is generated from one field-inducing line rather than two field-inducing lines. Even though less effective magnetic field is applied to these disturbed cells, variations within the magnetic junctions may allow the magnetic field induced by one current carrying line to switch the magnetization directions of one or more of the disturbed cells. In this manner, the write selectivity of the array may be reduced. Write selectivity, as used herein, may refer to the relative difference (i.e., current margin) between the amount of current responsible for switching the magnetization of a disturbed cell and the amount of current needed to switch the magnetization of a selected cell. Consequently, a reduction in write selectivity reduces the tolerance of the current used to reliably switch selected cells without switching disturbed cells within an array. In some cases, the tolerance may too small, allowing a false bit to be unintentionally written to one or more of the disturbed cells and in turn, decreasing the functionality of the array.
In addition, the number of memory cells arranged within an array may be limited by the arrangement of the conductive lines spanning across the columns and rows of the array. In general, the voltage required to generate a desired amount of current along a conductive line increases as the length of a conductive line increases, due to the current-resistance (IR) drop along the line. Since it is desirable to limit the overall power requirements of an array and, therefore, the amount of voltage used to operate the array, the conductive lines are generally restricted in length. In addition, the maximum voltage that may be used to operate an array may be restricted by the voltage supply coupled to the array, independent of the length of the conductive lines. Consequently, the number of magnetic junctions within an array is limited. In some cases, such a restriction causes the desired number of cells for a memory chip to be arranged within multiple arrays. Such an arrangement of cells, however, undesirably occupies a larger area of the wafer, increasing the size of the chip. As a result, fewer chips may be fabricated on the wafer, causing fabrication costs to increase and production throughput to decrease.
Therefore, it would be advantageous to develop a magnetic memory array with a configuration that reduces the effect of IR drop on the size of a memory array. In particular, it may be advantageous to fabricate a magnetic memory array with a configuration that eliminates IR drop as a limiting factor for the number of memory cells arranged along at least one dimension of an array. Such an array may advantageously increase the density of memory cells, thereby increasing the number of chips fabricated on a wafer of a particular size. In addition, it would be advantageous to develop a magnetic memory array with a configuration that increases the write selectivity of a magnetic memory array. More specifically, it would be advantageous to develop a magnetic memory array with a configuration that eliminates the issue of write selectivity.
The problems outlined above may be in large part addressed by a memory array that includes a conductive line adapted to induce a magnetic field around less than all of the magnetic memory junctions arranged along a row or a column of the array. In particular, the memory array may be adapted to selectively enable current to flow to the conductive line and one or more additional conductive lines aligned along a single row or column of the array comprising the conductive line. In this manner, the conductive line may be arranged adjacent to less than all of the magnetic junctions arranged along a row or column of the array. In other words, although each of the magnetic cell junctions of the array may be arranged adjacent to at least one respective field-inducing line with which to set the logic states of the junctions, not all of the magnetic cell junctions arranged along a single row or column are necessarily arranged adjacent to the same field-inducing line. In this manner, the memory array may include a plurality of field-inducing lines arranged along a single row or column of the array.
In some embodiments, the conductive line may be adapted to induce a magnetic field around more than two magnetic memory cell junctions. Alternatively, the conductive line may be adapted to induce a magnetic field around no more than two magnetic memory cell junctions. For example, the conductive line may be adapted to induce a magnetic field around a differential pair of magnetic memory cell junctions. In such an embodiment, the conductive line may be adapted to induce a relatively high level of resistance within one magnetic memory cell junction and a relatively low level of resistance within another magnetic memory cell junction. In other cases, the conductive line may be adapted to induce a magnetic field around magnetic memory cell junctions of a single memory array in which the resistance of individual magnetic memory cell junctions are compared to a common reference cell arranged along a row or column of the array. In either case, the conductive line, in some embodiments, may be configured to induce a magnetic field exclusively around the magnetic memory cell junctions of a single memory cell.
In some cases, the conductive line may include a first portion vertically aligned with one of a plurality of magnetic memory cell junctions arranged along a row of the memory array and a second portion vertically aligned with another of the plurality of magnetic memory cell junctions. In some embodiments, the second portion may be positioned such that a direction of current flow through the second portion is different than a direction of current flow through the first portion. More specifically, the second portion may be positioned such that the direction of current flow through the second portion is at an angle less than or equal to approximately 180xc2x0 relative to the direction of current flow through the first portion. In some cases, the direction of current flow through the second portion may be at an angle between approximately 60xc2x0 and approximately 120xc2x0 relative to the direction of current flow through the first portion. More particularly, the direction of current flow through the second portion may be approximately 90xc2x0 relative to the direction of current flow through the first portion in some cases. In addition or alternatively, the direction of current flow through the first portion may be arranged between easy and hard axes of the magnetic memory cell junction aligned with the first portion. Similarly, the direction of current flow through the second portion may be addition or alternatively arranged between easy and hard axes of the magnetic memory cell junction aligned with the second portion.
In general, the conductive line described herein may be configured to induce a magnetic field that changes the overall direction of a plurality of magnetic vectors arranged in an equilibrium state within a magnetic junction of the memory array. In particular, the conductive line may be arranged in electrical contact with some of the magnetic cell junctions of the memory array and, therefore, may serve as a bit line in some embodiments. Alternatively, the conductive line may serve as a digit line and be vertically spaced from the magnetic cell junctions of the memory array. In some embodiments, the conductive line may be further adapted to induce a magnetic field that changes the overall direction of a plurality of magnetic vectors arranged in an equilibrium state within another magnetic junction of the memory array. In such an embodiment, the magnetic junctions switched by the magnetic field may include a differential pair of magnetic memory junctions. Consequently, the conductive line may be adapted to set magnetic memory cell junctions in different logic states than each other.
A method for operating a magnetic memory array is also contemplated herein. In particular, the method may include flowing current in alignment with a dimension of the magnetic memory array and adjacent to less than all of the magnetic memory cell junctions arranged along a row or a column of the array aligned with the dimension. More specifically, the method may include enabling current flow from a source line to a conductive line aligned with the row or column of the array. Such a step of flowing current may be during a write operation and/or a read operation of the memory array. In some embodiments, the memory array may include a transistor adapted to enable current flow through the conductive line during such an operation. In particular, the step of enabling current flow for the method described herein may include applying voltage to a gate of a transistor coupled to the conductive line during a write operation of the memory array. In some cases, the memory array described herein may further include an additional transistor adapted to enable current flow from the conductive line through the magnetic junction during a read operation of the memory array. As such, the method described herein may include applying voltage to a gate of the additional transistor of the memory array during a read operation of the array.
There may be several advantages for fabricating the memory array described herein. In particular, the arrangement of a field-inducing line adjacent to less than all of the magnetic junctions aligned along a single row or column of a memory array may advantageously allow a higher density memory array to be fabricated. More specifically, the arrangement of several conductive lines along a single row or column of an array may negate IR drop as a limiting factor for the number of cells fabricated along one dimension of a memory array. Consequently, a higher density memory cell array may be fabricated. In addition, the reliability of magnetic memory arrays may be improved by the configuration of the conductive line described herein. More specifically, write selectivity of cells within an array may be increased, improving the reliability of the array.